1. Field of the Invention
The present invention relates to a configuration terminal for integrated devices. The invention also relates to a method for configuring an integrated device.
2. Description of the Related Art
As it is well known in the field of semiconductor integrated devices, there is often the need of configuring, in an optional way, devices sharing a fundamental structure.
In particular, such configuration flexibility of the integrated devices occurs each time a single configuration or layout is to be used, and when, in the meantime, what follows is to be considered:
as many functionalities as possible for the devices thus configured;
providing higher capacity for a base device, such as a memory device;
arranging multiple assemblies of integrated devices and in particular of chips on more levels (to obtain the so-called stacked structures);
allowing a single device a greater configuration flexibility (for example to allow an exchange of its contact terminals or pads).
For example, using such a configuration is known in a case having a memory cut off greater than the one technologically possible.
In such case, a plurality of elementary memory devices integrated with the technology available (and thus of smaller dimensions than what desired) is assembled in a stacked structure for realizing a memory of greater dimensions and possible expansions thereof. Such elementary memory devices are thus provided with address pads and additional “configuration” pads. In particular, such additional configuration pads are used for “sensitizing”, in combination with the additional address pads, the activation of a single elementary memory device among the ones in the stacked structure.
It is also known that when the expansion is greater than 2 (4, 8 . . . ) more additional configuration pads are to be provided.
The presence of configuration pads conditions the memory device layout since such configuration pads should be placed between the terminals or pins of the voltage references used, in particular the supply voltage reference Vdd and ground Gnd. More specifically, the configuration pads are to be placed in a central position with respect to such supply pins. In this way, for each additional configuration pad also an additional supply pin is to be added, connected to ground Gnd or to the supply voltage reference Vdd, for allowing the correct positioning of the additional configuration pads.
An example of layout of an integrated device provided with additional address and configuration pads is schematically shown in FIG. 1, globally indicated with 10.
The device 10 has a first P1 and a second supply pin P2, as well as an additional supply pin P3. In particular, in the example shown in the figure, the first supply pin P1 is connected to the supply voltage Vdd, the second supply pin P2 is connected to the ground Gnd and the additional supply pin P3 is connected to the supply voltage Vdd.
The device 10 also has n address pads A0 . . . An dedicated to the normal operation of the device itself, as well as a first An+1 and a second An+2 additional address pads connected to corresponding first Bn+1 and second Bn+2 additional configuration pads introduced for realizing an expansion of the device 10. Although in the example of FIG. 1 only two additional configuration and address pads are indicated, it is clear that it is possible to consider any number of such additional pads, according to the configuration needs of the device at issue.
In particular, the first additional configuration pad Bn+1 is used for sensitizing the first additional address pad An+1 on a high level, or equivalently low, to a configuration signal received. It is also possible to associate a different configuration of the device with said high and low values of the configuration signal on the additional configuration pad Bn+1. As shown in the figure, it is possible to place such first additional configuration pad Bn+1 between the supply and ground pins, P1 and P2 respectively, normally present in any integrated device, respecting the central positioning constraints for said configuration pads.
The presence of a second additional configuration pad Bn+2 however causes the addition of the additional supply pin P3 for enabling a correct positioning of such additional configuration pad Bn+2 between the second supply pin P2 and such additional supply pin P3, as shown in FIG. 1.
It is thus obvious that when the number of additional address pads of the integrated device increases a corresponding increase of the number of additional configuration pads is to be provided, which in turn causes the introduction of a congruous number of additional supply pins.
It is immediate to verify that, in the case of a great number of configuration pads, the hypothesis of feasibility becomes problematic and, in addition, its implementation is expensive and penalizing.
In the case of implementations of more functionalities of an integrated device, resorting to Option_Mask solutions is alternatively known for the configuration step of the device itself, which, however, imply a further expense increase due to the cost of the masks and to their management, as well as the introduction of a corresponding additional process step.
In the case of expansions of an integrated device by means of structures of the Stacked type, the traditional approach of connection by means of leads or metallic wires (the so called “Bonding”) is also complex, often tied to conditions of feasibility and in any case affected by complications of the bonding operation.
FIG. 2 shows, by way of example, a possible connection by means of bonding of a stacked structure 20. It is clear how the connection of single pads Tn of different levels L1 . . . Ln of the stacked device 20 by using a plurality of connection wires Wn to the common supply pins Pn requires an accurate planning of the positioning of such pads Tn and of the connection wires Wn to avoid that accidental contacts between such wires jeopardize the correct operation of the stacked structure 20 once assembled, although the case considered is the most favorable case in terms of position and number of pads at stake.
The above limitations and complications strongly affect, in the devices realized according to the prior art, both the “extended multi_configurability” and the essential one. It is important to remark that the available configurabilities are not only of the “expansion” or “multi-stacked” type as in the case of memory device but also of the “functional” type. The complexity associated with their implementations in practice limits and/or does not recommend the use thereof.